For various serial interfaces, such as Serial ATA (SATA), Serial Attached small computer system interface (SCSI) (SAS), PCIe, Fibre-Channel, ten gigabit attachment unit interface (XAUI), where 8b10b encoding is used for signaling, it is necessary to decipher whether the interface is in a valid signal-level state. Squelch Detector circuits are often used in conjunction with the High-Speed receiver circuits to detect these various signaling levels and states.
At the physical layer level, signaling can be classified as “In-Band”, “Out-of-Band”, and “Link-Down” (Disconnected or powered down). In-Band signaling is used for normal data transfer operations, and Out-of-Band signaling is used for various Reset, Wake-up, and other asynchronous operations that do not need the high-speed receiver and Clock/Data Recovery Circuits to be “locked-on” to the incoming serial data stream.
As the squelch detector circuit is intended to detect signaling levels, rather than to decipher the incoming serial bit-stream, it can achieve its design objectives with a lower bandwidth performance than the high-speed receiver. In optimizing these circuits for low-power operations, it is an acceptable performance/power compromise to have process, voltage, temperature (PVT) variations for the detector circuit threshold within a prescribed range.
As this detector circuit threshold will vary, additional circuitry and respective detection algorithms are highly desirable to ensure robust detection of the signaling levels, and link states.
The definition of an 8b/10b transmission code is identical to that specified in ANSI X3.230-1994, Clause 11 (and also IEEE 802.3Z, 36.2.4, July 1998). Using this scheme, 8 bit characters and one control bit are treated as 3 bits and 5 bits, mapped onto a 4 bit group code and a 6 bit group code, respectively. The control bit, in conjunction with the data characters is used to identify when to encode one of the 12 special symbols included in the 8b/10b transmission. As such, these code groups are concatenated to form a 10 bit symbol, which is transmitted from a transmitter to a corresponding receiver via a dual differential link.
The 8b/10b code also provides a scheme which is DC balanced, indicating that the generated code stream, or bit stream, includes a balanced number of 1 and 0 bits. In addition, the code ensures a limited run length, such that no more than five consecutive ones, “1”, or zeros, “0”, and a guaranteed transition density which permits clock recovery from the data stream. Accordingly, the combination of these features allows the receiving end of an encoded 8b/10b data stream to extract the bit rate clock to determine symbol (and packet) boundaries and to detect most transmission errors. Likewise, 8b/10b codes include the concept of disparity, wherein the disparity of any block of data is defined as the difference between the number of ones and the number of zeros. As such, positive and negative refer to an excess of ones over zeros or zeros over ones, respectively. Consequently, the code scheme guarantees that an encoded symbol's disparity is always either zero (11111, 00000), plus two (111111, 0000) or −2 (1111, 000000), which is quite useful for error detection.